In full bridge DC-DC power conversion architectures, one major challenge is that the maximum magnitude of low frequency oscillation on the secondary side should not exceed the drain-source breakdown voltage (Vds) of the power switch devices. The same challenge applies to half bridge DC-DC power conversion architectures. For most applications, a Resister-Diode-Capacitor (RDC) clamping circuit is an effective way to damp the oscillation magnitude without interruption of the regulation loop. The RDC clamping circuit is typically implemented on a power supply printed circuit board (PCB) using discrete components. For applications with a wide range of input voltages, such as telecommunication requiring 36-72V input voltage, the RDC clamping circuit design has to take the worst case into consideration so that the power switch devices will not experience Vds breakdown. As a result, the components making up the RDC clamping circuit have to be far larger than what required in most applications. Also, the generated power loss is larger than necessary, which may impact efficiency and thermal performance.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.